1. Field of the Invention
The present invention relates to a CMOS digital circuit having a body biasing control circuit to compensate for nonuniformity and changes in threshold voltages caused by defects in semiconductor manufacturing processes. In addition, the present invention also relates to the reduction of leakage current generated in the body biasing control circuit during operation.
This U.S. non-provisional patent application claims priority under 35, U.S.C § 119, of Korean Patent Application No. 10-2006-0085301, filed on Sep. 5, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
In the field of digital circuit technology, recent research is focused on integrating many functions in a single chip and achieving high performance while minimizing power consumption. In order to reduce power consumption, operating voltages must be lowered. However, the reduction of operating voltages causes two problems. First, when an operating voltage is reduced, the threshold voltage must also be reduced in order to compensate for decreased circuit speed. This reduction of the threshold voltage significantly increases the leakage current. The leakage current continuously flows even when the circuit does not operate. This leakage current is particularly problematic in circuits having a standby period longer than an operating period such as those used in mobile phones, PDAs, etc.
Another problem arises when the speed is lowered due to nonuniformity and changes in threshold voltages caused by faulty semiconductor manufacturing processes. A threshold voltage depends, in part, on semiconductor manufacturing processes. The lower an operating voltage, the greater the change in threshold voltage has on circuit speed. That is, when a change in threshold voltage is generated, the speed of a circuit changes within an allowable range at a high operating voltage, but the speed of the circuit can deviate from the allowable range at a low operating voltage. This significantly reduces semiconductor manufacturing yield resulting in increased manufacturing costs.
In order to resolve these problems, an adaptive body biasing method has been developed. An exemplary adaptive body biasing method is disclosed in U.S. Patent Application Publication No. 2006/0066388.
FIG. 1 illustrates a PMOS transistor used in a CMOS circuit, and FIG. 2 illustrates a NMOS transistor used in a CMOS circuit. The PMOS transistor and the NMOS transistor each include a gate G, a drain D, a source S, and a body terminal B. In a conventional CMOS circuit, a body terminal B of an NMOS transistor is connected to a ground and a body terminal B of a PMOS transistor is connected to a terminal with a predetermined voltage such as a supply voltage. When a different voltage is applied to the body terminal B, a threshold voltage of the NMOS or PMOS transistor changes. If a reverse bias voltage is applied between the body terminal B and the source terminal S, a threshold voltage increases which causes the speed of the CMOS circuit to decrease thereby reducing the leakage current. If a forward bias voltage is applied between the body terminal B and the source terminal S, the threshold voltage decreases which causes the speed of the CMOS circuit to decrease and the leakage current to be reduced. The adaptive body biasing method arguably resolves the leakage current problem and the threshold voltage nonuniformity problem generated in the semiconductor manufacturing process using the above-described characteristics. By applying a forward bias voltage between a body terminal B and a source terminal S in circuits having a high threshold voltage, it is possible to reduce a threshold voltage and obtain a desired circuit speed. By applying a reverse bias voltage in circuits having a low threshold voltage, it's possible to reduce a leakage current while maintaining an appropriate circuit speed. By applying a very high reverse bias current when the circuits are not in operation, it is possible to prevent leakage current flow.
FIG. 3 is a block diagram of a conventional adaptive body biasing circuit including a monitoring circuit 31, a bias generator 33, and a target circuit 35. Monitoring circuit 31 checks a threshold voltage of target circuit 35. If the threshold voltage of the target circuit 35 is lower than a desired threshold voltage, the bias generator 33 changes the body voltage (VBODY) of target circuit 35 which slightly increases the threshold voltage. If the threshold voltage of the target circuit 35 is higher than the desired threshold voltage, bias generator 33 changes the body voltage VBODY of the target circuit 35 which slightly decreases the threshold voltage. By repeatedly performing this operation, a desired threshold voltage of the target circuit 35 can be obtained.
However, drawbacks associated with such a conventional adaptive body bias circuit described above include a need for increased semiconductor area because monitoring circuit 31 and bias generator 33 occupy a large area; increased power consumption by the biasing circuit; and the time required for biasing is relatively long. Accordingly, the conventional adaptive body biasing circuit may be used in a large-sized CMOS circuit, but cannot be used independently in small macro blocks in a semiconductor chip. Also, in order to independently bias several macro blocks, monitoring circuits and bias generators corresponding to the number of macro blocks are required which greatly increases circuit overhead.
Accordingly, there is a need for a body biasing control circuit having a relatively small size when implemented as an integrated circuit and a body biasing circuit capable of being shared by a plurality of macro blocks and which can independently control body voltages of a plurality of macro blocks.